Programmable Logic Engineer (FPGA Execution) Job Listing at AMD in Taipei (Job ID 80374-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

The Role:

We are seeking a high-caliber FPGA Design Engineer to develop our next-generation IO-based connectivity systems. drive the design from initial concept through to hardware validation.

Key Responsibilities:

• System Architecture & Implementation: Lead the design, documentation, and implementation of complex IO-based connectivity systems, ensuring high-speed data integrity and system reliability.
• Front-End Methodology Leadership: Drive advanced RTL design flows, including resource optimization (Area/Power), multi-clock domain crossing (CDC) analysis, and reset domain crossing (RDC) strategies.
• Technical Documentation & Lifecycle Management: Synthesize comprehensive Requirement Specifications, Design Specs, and Test Plans. You will ensure these documents account for complex interactions between hardware, firmware, and software drivers.
• Cross-Functional Collaboration: Partner closely with Architects, Hardware Engineers, and Firmware teams to define feature sets, negotiate interfaces, and ensure seamless system integration.

Required Technical Qualifications:

• Xilinx Expertise: Minimum of 6 years of hands-on experience in RTL design with a deep-seated understanding of AMD-Xilinx UltraScale+ FPGA architectures.
• Toolchain Proficiency: Expert-level command of the Vivado Design Suite (Synthesis, Implementation, and Timing Closure).
• System-Level Architecture: Proven track record with high-speed bus protocols (AXI4/AXI-Stream), memory controllers, and interconnect bridges.
• High-Speed Connectivity: Direct experience implementing and debugging one or more high-speed protocols: PCIe (Gen3/4/5), 10/25/100G Ethernet, TCP/IP offload engines, or USB 3.x.
• Verification & Debug: Proficient in RTL simulation (Xcelium, Questa, or Vivado Simulator) and hardware-in-the-loop debugging using Xilinx ChipScope/ILA.

Professional Attributes:

• Ownership: A self-starting mindset with the ability to navigate ambiguity and independently drive tasks to production-ready completion.
• Problem-Solving: Exceptional analytical skills for triaging complex system-level hardware/software bugs.
• Communication: Ability to articulate technical trade-offs to both technical and non-technical stakeholders.

Academic Credentials:

• Bachelor's or Master's degree in electrical/computer engineering or related field preferred.

Location: Taipei Taiwan

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.