SDC, Synthesis and STA Engineer Job Listing at AMD in Hyderabad, TS (Job ID 76267-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

SDC, Synthesis and STA Engineer 

THE ROLE: 

The focus of this role is to plan and execute the front end implementation of IPs and its closure. This involves ownership of SDC development, SDC generation, verification, promotion/demotion and equivalence checking. The role might also epxand to (if needed) synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. Guide team members on technical issues.

KEY RESPONSIBILITIES:  

• Main responsibility is to own constratins, SDC developement for IPs, SS and SoCs. Including SDC generation, verification, promotion, demotion and equivalence using third party or self built tools. 
• Additonal responsibilities for front end implementation of IPs might include synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure
• Collaborate with designer and PNR teams to achieve closure. 
• Understand duration required, plan and execute as per schedule.
• Complete quality delivery for synthesis and timing closure.
• Debug and resolve technical issues

PREFERRED EXPERIENCE:  

• Existing SDC, constraints development with or without using fisthail, excellicon or TCM. 
• Experienced in synthesis, LEC, CLP and timing closure
• Preferred top level or SOC level experience
• Have handled blocks with complex designs, high frequency clocks and complex clocking
• complete understanding of timing constraints, low power aspects and concepts of DFT
• Have debug experience to solve issues.
• Interst in AI, Scripting and automation

ACADEMIC CREDENTIALS:  

• Bachelors with 8 years of experience or Masters degree with 6 years of experience in Electrical Engineering

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.