Static Timing Analysis Engineer Job Listing at AMD in Markham, ON (Job ID 67062-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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AMD is looking for a talented individual to join the Wired IP and Solutions Group (WISG) in the position of MTS Silicon Design Engineer. 

THE ROLE: 

An ASIC STA role in our System on Chip (SoC) design team, where numerous subsystems and IP cores are integrated to produce high performance SoC products. Our designers work on SoC level RTL design, block level RTL design, and/or subsystem level integration for a variety of SoC products.  Your expertise will be deployed in SoC ASIC projects targeting networking, security, storage, and other applications. 

THE PERSON: 

You are an experienced Static Timing Analysis (STA) engineer who has a passion for modern digital ASIC design. You are a team player who has excellent written and verbal communication skills with experience collaborating across multiple design sites and time zones. You have strong analytical and problem-solving skills and enjoy tackling new challenges.  You pay attention to details. You enjoy working amongst a multi-disciplinary team of professionals with diverse skills and experiences to complete projects in an efficient manner. 

KEY RESPONSIBILITIES:  

• Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs.
• Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management
• Engaging closely with block and SoC design teams to understand the design requirements, STA constraints, and convergence challenges.
• Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failure.

PREFERRED EXPERIENCE:  

• Experienced professional in ASIC implementation and CAD methodology, preferably experience closing timing of high-performance designs.
• Demonstrated ability in areas of ASIC STA constraints generation, timing analysis, timing convergence, and ECOs, at both block and full chip level, is a must
• Implementation experience and knowledge handling multi-voltage design is expected. STA closure of low power and multi-power mode designs is an added advantage.
• Expertise in industry standard ASIC EDA tools, including Synopsys DC and Primetime is required.
• Proficiency in scripting language, such as, TCL, Perl and/or Python
• Experience developing scripts to automate design flow, analysis
• Hands-on experience with Physical Design implementation is a plus
• Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
• Strong analytical/problem solving skills and pronounced attention to details.

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in Computer/Electrical Engineering  

LOCATION: Markham, ON; Ottawa, ON a possibility

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.