Adaptive Computing Group, Backend Design lead Job Listing at AMD in Bengaluru, KA (Job ID 62943-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

Adaptive Computing Group,  Backend Design lead 

THE ROLE:

As the one of the design leads of the Programmable Clock & Methodologies team in India for AMD's Adaptive-Embedded Computing products, you will be responsible for driving the development of clocking solutions that meet the high standards of AMD's AECG products. This will involve leading a team of highly skilled engineers in India, as well as collaborating with the global Clock team of experts at the San Jose office, inventing and implementing original solutions, addressing challenging clock problems in some of the industry's largest and most complex SOCs.

Every new Adaptive SOC brings a new set of programable Clock challenges with their latest system and functional architectures and their adoption of new semiconductor and packaging technologies. The Global Clock team works closely with functional Architecture, Programable fabric, Integration and SW teams to craft and implement new clock solutions, including new architectures, Clock IPs and development of new tools, flows & Methodology.

THE PERSON:

You will lead by bringing people together and drive towards consensus, decisions, and results. Working independently, you will convert high level concepts down to tangible specifications that can be implemented efficiently. You should enjoy collaborating with engineers with their diverse skillsets and bring their expertise to bear on solving challenging Programable Clock problems.

KEY RESPONSIBILITIES:

• Lead floor-planning, placement, routing, custom clock tree design, and optimization.
• Expert knowledge and hands-on experience of the entire backend and adjacent flows, including synthesis, Floor-planning P&R, clocking, timing closure, power and IO planning
• Perform all aspects of design flow from feasibility analysis, logic synthesis, FP, place and route, FEV, power, timing, quality checks, and design closure.
• Collaborate with design, Physical design, IT/infrastructure teams to ensure successful CAD flow all the way from IP design to SoC/3DIC design.
• Developing Programable global Clock distribution methodologies, optimizing Clock - Skew, Signal integrity and power integrity issues for AMD's next generation of programmable product families.

• Large Scale Block to Block Clock timing analysis, within the Die & Die to Die Clock interposer crossing.
• Deep analysis of timing paths to identify and debug key issues.
• Collaborate with functional IP teams (RTL, Ckt, physical design, Full Chip Timing, Integration) during the implementation and qualification of a growing number of programable Clock IPs.

PREFERRED EXPERIENCE:

• You should have a deep understanding of clocking methodologies and experience in leading teams to deliver complex projects. Working knowledge of Programable clocking is a plus.
• Strong working knowledge in all aspects of Physical Design and Advanced Packaging (Professional Experience: 10+ years of hands-on experience in physical design and verification, with a proven track record in chip-level PNR and successful tapeouts of complex SoC designs).
• You should be an expert in the development of clocking solutions and have the ability to work effectively with global teams (USA & India) to ensure that on time product delivery with high quality is met.
• Strong Clock fundamentals (Clock switching and gating, synchronization, Clock skew balancing, Jitter, Fmax, DCD and CDC analysis).

• Familiarity with test, debug, yield, post-Silicon Validation & Characterization is a plus.

• Working experience of Package level Clock SIPI is a plus.

• Proficient in STA and methodologies for timing closure and have a good understanding of noise, cross-talk, Aging and OCV effects, among others.Defined timing/SDC and placement constraints for IPs.
• Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
• Familiarity with Verilog and system Verilog for design.

• Additionally, you should be a skilled communicator, able to provide technical guidance and mentorship to junior team members to help them develop their skills and advance their careers.

ACADEMIC CREDENTIALS:

• Bachelor or master degree in computer engineering/Electronics or Electrical Engineering with 8-12+ years of exp.

#LI-MK1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.